Computer-aided standard cell-based design has been developed for quickly designing large scale ICs such as application specific integrated circuits (ASICs). The standard cell is a circuit that has been pre-designed and pre-verified as a building block. Design technologies known as standard cell library use different types of such building blocks. Each distinct standard cell in a library may have unique geometries of active, gate, and metal levels. Examples of a standard cell include an inverter, a NAND gate, a NOR gate, a Boolean function gate, a flip flop, and other similar logic circuits.
In any digital block implementation, the performance and speed of a digital block is mainly determined by high drive standard cells in a standard cell library. In advanced technology nodes, parasitic capacitances and resistances play a major role in degrading the performance of the digital blocks. Due to these parasitic capacitances and resistances, the performance of multi-input standard cells is getting affected at advanced technology nodes especially 28 nm node and beyond. This has resulted in lesser usage of such multi-input standard cells, which are primarily area efficient, in the high-speed digital blocks. Moreover, during synthesis, the usability of such standard cells is determined by the worst path delay of the standard cell.